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Flexible static memory controller (FSMC)
Table 104. FSMC_BCRx bit fields
RM0008
Bit No.
31-15
14
13-10
9
8
7
6
5-4
3-2
1
0
Bit name
EXTMOD
WAITPOL
BURSTEN
FACCEN
MWID
MTYP
MUXEN
MBKEN
Value to set
0x0000
0x1
0x0
Meaningful only if bit 15 is 1
0x0
-
Set according to memory support
As needed
As needed
0x0
0x1
Table 105. FSMC_TCRx bit fields
Bit No.
31-30
29-28
27-16
15-8
7-4
3-0
Bit name
ACCMOD
DATAST
ADDHLD
ADDSET
Value to set
0x0
0x2
0x000
Duration of the second access phase (DATAST+3 HCLK cycles) in
read. This value cannot be 0 (minimum is 1)
Duration of the middle phase of the read access (ADDHLD+1 HCLK
cycles)
Duration of the first access phase (ADDSET+1 HCLK cycles) in
read.
Table 106. FSMC_BWTRx bit fields
428/995
Bit No.
31-30
29-28
27-16
15-8
7-4
3-0
Bit name
ACCMOD
DATAST
ADDHLD
ADDSET
Value to set
0x0
0x2
0x000
Duration of the second access phase (DATAST+1 HCLK cycles) in
write. This value cannot be 0 (minimum is 1)
Duration of the middle phase of the write access (ADDHLD+1 HCLK
cycles)
Duration of the first access phase (ADDSET+1 HCLK cycles) in write.
Doc ID 13902 Rev 9
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